1. Field of the Invention
The present invention relates to a memory device. In particular, the present invention provides a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a semiconductor device wherein an USG (undoped silicate glass) layer is utilized during a process of forming a capacitor to leave a hard mask layer and a polysilicon layer on the top surface of a peripheral circuit region, and then a plate electrode layer on the peripheral circuit region is removed in a subsequent process to prevent a cut fuse pattern from being oxidized, thereby improving device characteristics and reliability of the semiconductor device.
2. Discussion of the Related Art
FIGS. 1a through 1d are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
Referring to FIG. 1a, a barrier nitride film 17 is formed on the entire surface of a semiconductor substrate 10 having a lower structure such as a storage electrode contact plug 13 and a first interlayer insulating film 15, and then a first oxide film 20 and a nitride film (not shown) are sequentially deposited on the barrier nitride film 17. Next, the nitride film on a cell region 1000a is etched using a capacitor mask as an etching mask to form a nitride film pattern 35 exposing the first oxide film 20 in a capacitor region.
Referring to FIG. 1b, the exposed first oxide film 20 is etched using the nitride film pattern 30 as an etching mask to form a first oxide film pattern 25 defining the capacitor region.
Referring to FIG. 1c, the barrier nitride film 17 exposed in the capacitor region is etched to expose the lower structure, and then a lower electrode layer 60 is formed on the entire surface of the resultant. Next, a second oxide film 65 filling up the capacitor region is formed on the entire surface. A CMP process is performed until the first oxide film pattern 25 is exposed so as to remove the nitride film pattern 35.
Referring to FIG. 1d, the second oxide film 65 is removed to expose the lower electrode layer 60, and then a dielectric layer 70 and a plate electrode layer 80 are sequentially formed on the entire surface. Next, a planarized polysilicon layer 90 filling up at least the capacitor region is formed on the entire surface of the resultant. Thereafter, the polysilicon layer 90, the plate electrode layer 80 and the dielectric layer 70 on the peripheral circuit region 1000b adjacent to the cell region 1000a are etched by a predetermined width to expose the first oxide film pattern 25 on the peripheral circuit region 1000b. 
FIG. 2 is a cross-sectional view showing a cut fuse pattern of the semiconductor device according to the conventional method for manufacturing a semiconductor device.
Referring to FIG. 2, a fuse pattern (not shown) is formed on the peripheral circuit region 1000b according to the above conventional method for manufacturing a semiconductor device. A metal line 93 is formed in the fuse pattern serving as a repair fuse. When a circuit with a defect is found during a test process for the semiconductor device, the fuse pattern corresponding the fault circuit is cut using a laser in order to prevent the fault circuit from being worked. However, according to the conventional method for manufacturing a semiconductor device, the fuse pattern includes the plate electrode layer 80 made of a metal material such as TiN, W and Cu. In the case of the cut fuse pattern, the exposed plate electrode layer 80 is oxidized to degenerate the electric characteristic of a semiconductor device even in a normal circuit.
In order to solve such a problem, a metal line 97 for an oxidation stopper is further formed between the metal line 93 and the blown portion of the fuse pattern so as to prevent the oxidation of the plate electrode layer 70 exposed in the blown portion from causing the metal line 93. However, the metal line 97 for an oxidation stopper must have an additional formation process, thus lowering the yield of the semiconductor device.